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eorex em42am3284lbc jun. 2009 www.eorex.com 1/24 revision history revision 0.1 (mar. 2008) - first release. revision 0.2 (jun. 2009).. - add extend temperature grade (-25 c ~85 c) product. - add idd6 ?pasr? spec.(page 8)
eorex em42am3284lbc jun. 2009 www.eorex.com 2/24 512mb (4m 4bank 32) double data rate sdram features ? internal double-date-ra te architecture with 2 accesses per clock cycle. ? 1.8v 0.1v vdd/vddq ? 1.8v lv-coms compatible i/o ? burst length (b/l) of 2, 4, 8, 16 ? 3 clock read latency ? bi-directional,intermittent data strobe(dqs) ? all inputs except data and dm are sampled at the positive edge of the system clock. ? data mask (dm) for write data ? sequential & interleaved burst type available ? auto precharge option for each burst accesses ? dqs edge-aligned with data for read cycles ? dqs center-aligned with data for write cycles ? no dll;ck to dqs is not synchronized ? deep power down mode ? partial array self-refresh(pasr) ? auto temperature compensated self-refresh (tcsr) by built-in temperature sensor ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms description the em42am3284lbc is high speed synchronous graphic ram fabricated with ultra high performance cmos process containing 536,870,912 bits which organized as 4meg words x 4 banks by 32 bits. the 512mb ddr sdram uses a double data rate architecture to accomplish high-speed operation. the data path internally prefetches multiple bits and it transfers the datafor both rising and falling edges of the system clock.it means the doubled data bandwidth can be achieved at the i/o pins. available packages:tfbga-90b(13mmx10mm). ordering information part no organization max. freq package grade pb em42am3284lbc-75f 16m x 32 133mhz/ddr266 @cl3 tfbga-90b commercial free EM42AM3284LBC-6F 16m x 32 166mhz/ddr333 @cl3 tfbga-90b commercial free em42am3284lbc-75fe 16m x 32 133mhz/ddr266 @cl3 tfbga-90b extend temp. free EM42AM3284LBC-6Fe 16m x 32 166mhz/ddr333 @cl3 tfbga-90b extend temp. free
eorex em42am3284lbc jun. 2009 www.eorex.com 3/24 * eorex reserves the right to change products or specification without notice.
eorex em42am3284lbc jun. 2009 www.eorex.com 4/24 pin assignment 1 2 3 7 8 9 vss dq31 vssq a vddq dq16 vdd vddq dq29 dq30 b dq17 dq18 vssq vssq dq27 dq28 c dq19 dq20 vddq vddq dq25 dq26 d dq21 dq22 vssq vssq dqs3 dq24 e dq23 dqs2 vddq vdd dm3 nc f nc dm2 vss cke clk /clk g /we /cas /ras a9 a11 a12 h /cs ba0 ba1 a6 a7 a8 j a10 a0 a1 a4 dm1 a5 k a2 dm0 a3 vssq dqs1 dq8 l dq7 dqs0 vddq vddq dq9 dq10 m dq5 dq6 vssq vssq dq11 dq12 n dq3 dq4 vddq vddq dq13 dq14 p dq1 dq2 vssq vss dq15 vssq r vddq dq0 vdd 90ball tfbga / (13mm x 10mm x 1.2mm)
eorex em42am3284lbc jun. 2009 www.eorex.com 5/24 pin description (simplified) pin name function g2,g3 clk,/clk (system clock) clock input active on the positive rising edge except for dq and dm are active on both edge of the dqs. clk and /clk are differential clock inputs. h7 /cs (chip select) /cs enables the command decoder when ?l? and disable the command decoder when ?h?.the new command are over- looked when the command decoder is disabled but previous operation will still continue. g1 cke (clock enable) activates the clk when ?h? and deactivates when ?l?. when deactivate the clock,cke low signifies the power down or self refresh mode. j8,j9,k7,k9,k1, k3,j1~j3,h1~h3, a0~12 (address) row address (a0 to a12) and calumn address (ca0 to ca8) are multiplexed on the same pin. ca10 defines auto precharge at calumn address. h8,h9 ba0, ba1 (bank address) selects which bank is to be active. g9 /ras (row address strobe) latches row addresses on the posit ive rising edge of the clk with /ras ?l?. enables row access & pre-charge. g8 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. g7 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. l8,l2,e8,e2 dqs0~3 (data input/output) data inputs and outputs are synchronized with both edge of dqs. k8,k2,f8,f2 dm0~3 (data input/output mask) dm controls data inputs.dm0 corresponds to the data on dq0~dq7.dm1 corresponds to the data on dq8~dq15??.. r8,p7,p8,n7,n8,m7, m8,l7,l3,m2,m3,n2, n3,p2,p3,r2,a8,b7, b8,c7,c8,d7,d8,e7, e3,d2,d3,c2,c3,b2, b3,a2 dq0~31 (data input/output) data inputs and outputs are multiplexed on the same pin. a9,f1,r9/ a1,f9,r1 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuits. a7,b1,c9,d1,e9,l9, m1,n9,p1,r7/a3,b9, c1,d9,e1,l1,m9,n1, p9,r3 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. f3,f7 nc/rfu (no connection/reserved for future use) this pin is recommended to be left no connection on the device.
eorex em42am3284lbc jun. 2009 www.eorex.com 6/24 absolute maximum rating symbol item rating units v in , v out input, output voltage -0.5 ~ +2.3 v v dd , v ddq power supply voltage -0.5 ~ +2.3 v commercial 0 ~ +70 t op operating temperature range extended -25 ~ +85 c t stg storage temperature range -55 ~ +125 c p d power dissipation 1 w i os short circuit current 50 ma note: caution exposing the device to stress above thos e listed in absolute maximum ratings could cause permanent damage. the device is not m eant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. capacitance (v cc =1.8v 0.1v, f=1mhz, t a =25c) symbol parameter min. typ. max. units c clk clock capacitance 2.0 4.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml, dqmu 2.0 4.5 pf c o input/output capacitance 3.5 6.0 pf recommended dc operating conditions (t a =0c ~70c) symbol parameter min. typ. max. units v dd power supply voltage 1.7 1.8 1.9 v v ddq power supply voltage (for i/o buffer) 1.7 1.8 1.9 v v ih input logic high voltage 0.8* v ddq v ddq +0.3 v v il input logic low voltage -0.3 0.2*v ddq v note: * all voltages referred to v ss .
eorex em42am3284lbc jun. 2009 www.eorex.com 7/24 recommended dc operating conditions (v dd =1.8v 0.1v, t a =0c ~ 70c) max. symbol parameter test conditions -75 units i dd1 operating current (note 1) burst length=2, t rc t rc (min.), i ol =0ma, one bank active 80 ma i dd2p precharge standby current in power down mode cke v il (max.), t ck =min 1 ma i dd2n precharge standby current in non-power down mode cke v il (min.), t ck =min, /cs v ih (min.) input signals are changed one time during 2 clks 4 ma i dd3p active standby current in power down mode cke v il (max.), t ck =min 3 ma i dd3n active standby current in non-power down mode cke v ih (min.), t ck =min, /cs v ih (min.) input signals are changed one time during 2 clks 10 ma i dd4 operating current (burst mode) (note 2) t ck t ck (min.), i ol =0ma, all banks active 120 ma i dd5 refresh current (note 3) t rc t rfc (min.), all banks active 90 ma i dd6 self refresh current cke 0.2v 0.8 ma *all voltages referenced to v ss . note 1: i dd1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i dd4 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 3: min. of t rfc (auto refresh row cycle times) is shown at ac characteristics.
eorex em42am3284lbc jun. 2009 www.eorex.com 8/24 advanced data retention current (tj = ?25 to +85c, vdd and vddq = 1.7v to 1.9v, vss and vssq = 0v) symbol parameter conditions max. units pasr="000" (full) 300 ua pasr="001" (2bk) 250 ua i dd6 pasr="010" (1bk) -25c tj +40c cke 0.2v 220 ua pasr="000" (full) 560 ua pasr="001" (2bk) 390 ua i dd6 pasr="010" (1bk) +40c < tj +70c cke 0.2v 300 ua pasr="000" (full) 800 ua pasr="001" (2bk) 650 ua i dd6 pasr="010" (1bk) +70c < tj +85c cke 0.2v 500 ua recommended dc operating conditions (continued) symbol parameter test conditions min. typ. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v -2 +2 ua i ol output leakage current 0 v o v ddq , d out is disabled -1.5 +1.5 ua v oh high level output voltage i o =-0.1ma 0.9*v ddq v v ol low level output voltage i o =+0.1ma 0.1*v ddq v
eorex em42am3284lbc jun. 2009 www.eorex.com 9/24 block diagram row add. buffer row decoder address register auto/ self refresh counter memory array s/ a & i/ o gating col. decoder col. add. buffer mode register set col add. counter burst counter write dqm control data in data out doi a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 timing register clk cke /cs / ras / cas /we dm dm /clk dqs
eorex em42am3284lbc jun. 2009 www.eorex.com 10/24 ac operating test conditions (v dd =1.8v 0.1v, t a =0c ~70c) item conditions output reference level 0.9v/0.9v output load see diagram as below input signal level 1.6v/0.2v transition time of input signals 0.5ns input reference level 0.9v ac operating test characteristics (v dd =1.8v 0.1v, t a =0c ~70c) -6 -7.5 symbol parameter min. max. min. max. units t dqck dq output access from clk,/clk 2 5.5 2 6 ns t dqsck dqs output access from clk,/clk 2 5.5 2 6 ns t cl ,t ch cl low/high level width 0.45 0.55 0.45 0.55 t ck t ck clock cycle time ( cl3 ) 6 7.5 ns t dh ,t ds dq and dm hold/setup time 0.6 0.8 ns t dipw dq and dm input pulse width for each input 1.2 1.75 ns t hz ,t lz data out high/low impedance time from clk,/clk 1 5.5 1 6 ns t dqsq dqs-dq skew for associated dq signal 0.5 0.6 ns t dqss write command to first latching dqs transition 0.75 1.25 0.75 1.25 t ck t dsl ,t ds h dqs input valid window 0.2 0.2 t ck t mrd mode register set command cycle time 2 2 t ck t wpres write preamble setup time 0 0 ns t wpst write preamble 0.4 0.6 0.4 0.6 t ck t ih ,t is address/control input hold/setup time 1.1 1.3 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck
eorex em42am3284lbc jun. 2009 www.eorex.com 11/24 ac operating test characteristics (continued) (v dd =1.8v 0.1v, t a =0c ~70c) -6 -75 symbol parameter min. max. min. max. units t rpst read postamble 0.4 0.6 0.4 0.6 t ck t ras active to precharge command period 42 120k 45 120k ns t rc active to active command period 72 75 ns t rfc auto refresh row cycle time 90 108 ns t rcd active to read or write delay 24 30 ns t rp precharge command period 18 22.5 ns t rrd active bank a to b command period 12 15 ns t ccd column address to column address delay 1 1 t ck t cdlw last data in to write command 1 1 t ck t dpl last data in to precharge command 3 3 t ck t bstw burst stop to write delay 3 3 t ck t wpd write to pre-charge delay(same bank) 3+bl/2 3+bl/2 t ck t rpd read to pre-charge delay(same bank) bl/2 bl/2 t ck t srex exit self refresh to non-col. command 20 16 t ck t wtr internal write to read command delay 1 1 t ck t wrd write recovery 2 2 t ck t cke cke minimum pulse width 2 2 t ck t refi average periodic refresh interval 7.8 7.8 us
eorex em42am3284lbc jun. 2009 www.eorex.com 12/24 simplified state diagram
eorex em42am3284lbc jun. 2009 www.eorex.com 13/24 1. command truth table cke command symbol n-1 n /cs /ras /cas /we ba0, ba1 a10 a12~a0 ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre-charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre-charge writa h x l l h h v h v bank activate act h x l l h h v v v pre-charge select bank pre h x l l h l v l x pre-charge all banks pall h x l l h l x h x mode register set mrs h x l l l l l l v h = high level, l = low level, x = high or low level (don't care), v = valid data input 2. cke truth table cke item command symbol n-1 n /cs /ras /cas /we addr. idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x l h l h h h x self refresh self refresh exit l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x remark h = high level, l = low level, x = high or low level (don't care)
eorex em42am3284lbc jun. 2009 www.eorex.com 14/24 3. operative command table current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l x ba/ca/a10 read/writ/bw illegal (note 1) l l h h ba/ra act bank active,latch ra l l h l ba, a10 pre/prea nop (note 3) l l l h x refa auto refresh (note 4) idle l l l l op-code, mode-add mrs mode register h x x x x desl nop l h h h x nop nop l h h l ba/ca/a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba/ca/a10 writ/writa begin write,latch ca, determine auto-precharge l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea precharge/precharge all l l l h x refa illegal row active l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term terminal burst l h l h ba/ca/a10 read/reada terminate burst,latch ca, begin new read, determine auto-precharge l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst, prechare l l l h x refa illegal read l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l h ba/ca/a10 read/reada terminate burst with dm=?h?,latch ca,begin read,determine auto-precharge (note 2) l h l l ba/ca/a10 writ/writa terminate burst,latch ca,begin new write, determine auto-precharge (note 2) l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst with dm=?h?, precharge l l l h x refa illegal write l l l l op-code, mrs illegal
eorex em42am3284lbc jun. 2009 www.eorex.com 15/24 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba/ca/a10 term illegal l h l x ba/ra read/write illegal (note 1) l l h h ba/a10 act illegal (note 1) l l h l x pre/prea illegal (note 1) l l l h x refa illegal read with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal write with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea nop(idle after t rp ) (note 3) l l l h x refa illegal pre-charging l l l l op-code, mode-add mrs illegal h x x x x desl nop(row active after t rcd ) l h h h x nop nop(row active after t rcd ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal row activating l l l l op-code, mode-add mrs illegal remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge
eorex em42am3284lbc jun. 2009 www.eorex.com 16/24 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l h ba/ca/a10 read illegal (note 1) l h l l ba/ca/a10 writ/writa new write, determine ap l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal write recovering l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/writ illegal l l h h ba/ra act illegal l l h l ba/a10 pre/prea nop(idle after t rp ) l l l h x refa illegal refreshing l l l l op-code, mode-add mrs illegal remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 1: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 2: must satisfy bus contention, bus turn ar ound, and/or write recovery requirements. note 3: nop to bank precharging or in idle state.may precharge bank indicated by ba. note 4: illegal of any bank is not idle.
eorex em42am3284lbc jun. 2009 www.eorex.com 17/24 4. command truth table for cke cke current state n-1 n /cs /r /c /w addr. action h x x x x x x invalid l h h x x x x exist self-refresh l h l h h h x exist self-refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop(maintain self refresh) h x x x x x x invalid l h h x x x x exist power down l h l h h h x exist power down l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal both bank precharge power down l l x x x x x nop(maintain power down) h h x x x x x refer to function true table h l h x x x x enter power down mode (note 3) h l l h h h x enter power down mode (note 3) h l l h h l x illegal h l l h l x x illegal h l l l h h ra row active/bank active h l l l l h x enter self-refresh (note 3) h l l l l l op-code mode register access h l l l l l op-code special mode register access all banks idle l x x x x x x refer to current state any state other than listed above h h x x x x x refer to command truth table remark: h = high level, l = low level, x = high or low level (don't care) notes 1: after cke?s low to high transition to exist self refresh mode.and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. notes 2: cke low to high transition is asynchronous as if restarts internal clock. notes 3: power down and self refresh can be entered only from the idle state of all banks.
eorex em42am3284lbc jun. 2009 www.eorex.com 18/24 mode register definition mode register set the mode register stores the data for controlling the various operating m odes of ddr sdram which contains addressing mode, burst length, /cas lat ency, test mode, dll reset and various vendor s specific opinions. the defaults values of the register is not def ined, so the mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on /cs, /ras, /cas, /we and ba0 ( the ddr sdram should be in all bank prec harge with cke already high prior to writing into the mode register. ) the state of t he address pins a0-a12 in the same cycle as /cs, /ras, /cas, /we and ba0 going low is written in the mode register. two clock cycles are requested to complete the write operation in the mode register. the mode regi ster contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a0-a2, addressing mode uses a3, /cas latency ( read latency from column address ) uses a4-a6. a7 is used for test mode . a8 is used for ddr reset. a7 must be set to low for normal mrs operation.
eorex em42am3284lbc jun. 2009 www.eorex.com 19/24 address input for mode register set
eorex em42am3284lbc jun. 2009 www.eorex.com 20/24 burst type (a3) burst length a3 a2 a1 a0 sequential addressing interleave addressing x x x 0 0 1 0 1 2 x x x 1 1 0 1 0 x x 0 0 0 1 2 3 0 1 2 3 x x 0 1 1 2 3 0 1 0 3 2 x x 1 0 2 3 0 1 2 3 0 1 4 x x 1 1 3 0 1 2 3 2 1 0 x 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 x 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 x 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 x 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 x 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 x 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 x 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 0 0 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13 0 0 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 0 1 0 0 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 1 2 3 12 13 14 15 8 9 10 11 0 1 0 1 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 4 7 6 1 0 3 2 13 12 15 14 9 8 11 10 0 1 1 0 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 4 5 2 3 0 1 14 15 12 13 10 11 8 9 0 1 1 1 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 1 0 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 1 0 0 1 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 8 11 10 13 12 15 14 1 0 3 2 5 4 7 6 1 0 1 0 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 8 9 14 15 12 13 2 3 0 1 6 7 4 5 1 0 1 1 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 10 9 8 15 14 13 12 3 2 1 0 7 6 5 4 1 1 0 0 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 8 9 10 11 4 5 6 7 0 1 2 3 1 1 0 1 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 12 15 14 9 8 11 10 5 4 7 6 1 0 3 2 1 1 1 0 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 13 10 11 8 9 6 7 4 5 2 3 0 1 16 1 1 1 1 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * page length is a function of i/o organization and column addressing
eorex em42am3284lbc jun. 2009 www.eorex.com 21/24 extended mode register set ( emrs ) the extended mode register is written by asserti ng low on /cs, /ras, /cas, /we and high on ba1 ( the ddr sdram should be in all bank precharge with cke already prior to writing into the extended mode register. ) the state of address pins a0-a10 and ba1 in the same cycle as /cs, /ras, /cas, and /we going low is written in the extended mode register. the mo de register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. high on ba0 is used for emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation.
eorex em42am3284lbc jun. 2009 www.eorex.com 22/24 output drive strength the normal drive strength got all outputs is specified to be lv-cmos. by setting emrs specific parameter on a6 and a5, driving capability of data output drivers is selected. temperature compensated self-refresh tcsr controlled by programming in the extended mo de register (emrs). the memory automatically changes the self-refresh cycle by temperature fluctuations. partial array self refresh in emrs setting ,memory array size to be refreshed du ring self-refresh operation is programmable in order to reduce power. data outsi de the defined area will not be re tained during self-refresh.
eorex em42am3284lbc jun. 2009 www.eorex.com 23/24 package description
eorex em42am3284lbc jun. 2009 www.eorex.com 24/24

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